Fourth International Workshop on Design Automation: Russian Workshop '94 & Pan-European Seminar on Cooperation of European Research In Science, Technology And Education, Moscow, 27-29 June, 1994.

Organizing And Programme Committee:

• Daniel Auvergne, LIRMM/University of Montpellier II, France
  
• Tadeusz Grabowiecki, Silesian Technical University, Poland
  
• Egon Hoerbst, Siemens AG, Germany
  
• Igor Norenkov, "Bauman" Moscow State Technical University, Russia
  
• Antonio Nunez, CMA/University of Las Palmas de Gran Canaria, Spain
  
• Adam Pawlak, GMD-SET, Germany
  
• Wolfgang Rosenstiel, FZI/University of Tuebingen, Germany
  
• Gabriele Saucier, INPG/Institut National Politechnique de Grenoble, France
  
• Alexander Stempkovsky, Academy of Sciences of Russia - NIISAPRAN, Russia
  
• Klaus Woelcken, CEC/Commission of the European Communities, Belgium
  

The events were sponsored by:

• Commission of the European Communities;
  
• International Computer Initiative Scientific Centre
  
• IFIP TC 10
  
• IFIP WG 10.5
  
• Russian Academy of Sciences/OIVTA
  
• Moscow ACM SIGDA Local Chapter
  
• Ministry of the Russian Federation for Science and Technical Policy
  
• Presidential Committee of the Russian Federation for Informatization Policy
  
• TELECOM Stock Company
  

First (General) Session:
Cooperation of European Researches In Science, Technology And Education.

The main goals of the General Session were:

• To present the main guidelines and programmes of the European Communities in various scientific disciplines, technology and education;
  
• To review the possibilities of cooperation between European scientists in the frame of the programmes of the Commission of the European Communities and the International Association for the Promotion of Cooperation with Scientists from the Independent States of the Former Soviet Union.
  

Eleven reports were presented in frames of four subsessions:

Session 1 - "Co-operation Perspectives"

Session 2 - "Co-operation: Possibilities and Practice"

Session 3 - "Co-operation Project with Industrial Partners - a Real Challenge"

Session 4 - "How to Build a Pan-European Project"

Second Session: Cad Tools For Top-down Design Of Embedded Systems.

Eight reports were presented in frames of second session.

Third Session: VLSI Simulation & Optimization Methods For New Emerging Technologies

with the following topics:

• Timing Modeling And Circuit Optimization
  
• Power Modeling
  
• Layout Optimization
  
• Interconnect Modeling
  
• Computer Aided Design Systems
  

Twenty-one reports were presented in frames of third session.

Moreover, demo programs of the software of the Mentor Graphics Corp. were presented by representatives of the Mentor Graphics Corp. (Europe).

In addition, eight representatives of Russia took part in the work of the Secretariat of the Seminar and the Workshop.

Workshop and Seminar Final Program

Pan-European Seminar

General Session On Co-operation Of European Researchers In Science, Technology And Education

Monday Morning, June 27th

Opening session:

Session chair: Alexander L. Stempkovsky

• Opening, welcome and greeting aLIresses.
  
• Presentation of the programme of the General Session.
  
• Adam Pawlak, the General Session Organizer; ARTEMIS, Fourier University, France
  

Session 1: Co-operation Perspectives

Session chair: Alexander L. Stempkovsky

• Co-operation in Science and Technology, the Challenge for European Researchers. K. Woelcken, CEC, Belgium
  
• Promoting East-West Co-operation in Research and Development - the INTAS Experience. K. M. Krohn, INTAS, Belgium
  

Session 2: Co-operation: Possibilities and Practice

Session chair: Klaus Woelcken

• EUROCHIP - Stimulation of Training and Technology Transfer in Microelectronics. J. McLean, RAL, UK
  
• Your Dynamic University Research Team as Co-ordinator or Subcontractor in CEC Programmes: Enter the New Era of E-mail and News. A. M. Trullemans Lab. Microelectronique, Univ. Catholique de Louvain, Belgium
  
• Presentation of IFIP Activity. E. Hoerbst, Siemens AG, Germany, Chair of IFIP TC 10
  
• What is Participation of East European Partners in the European CAD Standardization Initiative? J. Mermet, Fourier University, ARTEMIS, France
  

Monday Afternoon, June 27th

Session 3: Co-operation project with industrial partners - a real challenge

Session chair: Alexander A.Vasenkov

• Examples and First Results in East-West Transfer of Technology in FTA-AULershof Especially with Respect to French-German-Russian Network. H. Neumann, Entwicklungsgesellschaft AULershof mbH, Germany
  
• Mentor Graphics, a Leader in Electronic Design Automation (and good platform for Technical Co-operation). K. Popp, Mentor Graphics Corp. (Europe)
  

Session 4: How to Build a Pan-European Project

Session chair: Adam Pawlak

• How to Get an Access to RTD Programmes. H. Schuh, ULR-IF/EG, France
  
• Network and Information Infrastructure for RTD Co-operation between the EU and Central and Eastern Europe - (Experience of two Recent COPERNICUS Projects: ESATT and INDIS Projects). W. Wittig, DFKG, Germany
  
• Collaboration with European Communities in JCF Project. V. M. Mikhov, Institute of Operating Systems, Russia
  
• Open Discussion
  

Tuesday morning, June 28th

Sessions A1, A2: CAD Tools for Top-Down Design of EmbeLIed Systems

Sessions chair: Prof. Wolfgang Rosenstiel

• Invited Report: EmbeLIed System Design: Status and New Challenges. W. Rosenstiel, FZI/University of Tuebingen, Germany
  
• Knowledge-Based System for Embedded Software Design. N. N. Sharipova, A. P. Zamjatin, E. A. Zavadskaja, Ural State University, Russia
  
• Toward Design of Complex Decomposable System. M. Sh. Levin Independent Consultant/Researcher, Russia
  
• HW/SW Co-Design: Future Requirements on Development Processes. N. M. Vitsyn, Russian EDIF Association, Russia
  
• BDD Application to Mutual Exclusion Testing in High-Level Synthesis. V. A. Syngaevsky, Russian Academy of Sciences/NIISAPRAN, Russia
  
• BDD Based Decomposition for Depth Reduction. A. I. Kornilov, T. Yu. Isaeva, Russian Academy of Sciences/NIISAPRAN, Russia
  
• Mentor Graphics Software for High Level Simulation and Synthesis. D. Wood, Mentor Graphics Corp. (Europe)
  
• Link between Low-level and High-level Synthesis. F. Poirot, Compass Design Automation, France
  

Tuesday afternoon, June 28th

Session B1: Timing Modeling and Circuit Optimization

Chair: Prof. Antonio Nunez

• Delay Performance Modeling on Pseudo-NMOS Structures. D. Deschacht, D. Auvergne University of Montpellier II, France
  
• Optimization of CMOS Circuits Based on Parameterized Cells. A. L. Glebov, A. A. Lialinsky, S. G. Rusakov, Russian Academy of Sciences/NIISAPRAN, Russia
  
• Circuit Optimization with the Aid of Quasi Electrical Circuit Simulation. G. S. Temkin, Research Institute of Molecular Electronics, Russia
  
• General Determination of Buffer Insertion Limits. M. Mellah, N. Azemard, D. Auvergne University of Montpellier II, France
  

Session B2: Timing Analysis and Circuit Optimization II

Session chair: Prof. Joan Figueras

• A New Approach on Searching for Sizing and Timing Relations for GaAs DCFL. J. A. Montiel, J. F. Lopez, V. Armas, R. Sarmiento, A. Nunez, University of Las Palmas, Spain
  
• Multilevel Digital Simulator with Account of the Delays Ambiguities. S. A. Linetsky, Scientific Research Institute of Computing Machinery, Russia
  
• Statistical Models for Design Verification. N. A. Akbulatov, I. I. Solovay, A. B. Svyatsky, Scientific and Research Centre of Computer Technology, Russia
  
• BLI Based Algorithm for Series-Parallel Network Representation and Manipulation. A. L. Glebov, Russian Academy of Sciences/NIISAPRAN, Russia
  

Wednesday morning, June 29th

Session B3: Power Modeling.

Session chair: Prof. Wolfgang Nebel * * Co-chair: Prof. Konstantin O. Petrosyants

• Models for Power Dissipation of ASIC Cells. W. Nebel, University of Oldenburg, Germany
  
• Extra Power Consumed in Static CMOS Circuits due to Unnecessary Logic Transitions. M. A. Ortega, J. Figueras, Technical University of Catalunya, Spain
  
• A New Power Consumption Estimation Methodology for Digital Circuits. W. Roethig, Telecom, France
  
• Power Efficient Layout Methodology. F. Moraes, M. Robert, D. Auvergne, University of Montpellier II, France
  

Session B4: Layout Optimization

Session chair: Prof. Igor P. Norenkov

• Detail Layout Optimization for Standard Cells of Arbitrary Height. S. V. Gavrilov, E. G. Gorlatch, "Firm Razvitie" Ltd, Russia
  
• Evolutionary Wiring Method for Full Custom VLSI Design. A. M. Marchenko, Moscow State Institute of Electronic Engineering, Russia
  
• Analog/Mixed Signal Solutions from Mentor Graphics for IC, ASIC and PSB. D. Wood, Mentor Graphics Corp. (Europe)
  

Wednesday afternoon, June 29th

Session B5: Interconnect Modeling

Session chair: Prof. Daniel Auvergne

• Interconnect Delay Model with Performance Optimization Emphasis. D. Deschacht, C. Dabrin, D. Auvergne, University of Montpellier II, France
  
• Implementation of Time-Stepping Method for Analysis of Single and MulticonductorTransmission Lines. A. V. Artemenkov, Russian Academy of Sciences/NIISAPRAN, Russia
  
• Methods and Algorithms for Simulation of High - Speed Interconnects. V. L. Lantsov, A. G. Dolinin, Vladimir-city Technical University, Russia
  

Session B6: Computer Aided Design Systems

Session chair: Dr. Sergej G. Rusakov

• A System for Design Verification and Automated Test Development: Concepts and Implementation. A. G. Birger R&D Corporation "Almaz", Russia
  
• A Teaching System for Top-Down VLSI Design. A. M. Bershchadsky, I. G. Krevsky, Penza-city State Technical University, Russia
  
• New Generation of CAD System for High Performance Digital and Digital-Analog VLSI Simulation. V. N. Perminov, V. V. Shumilov, D. V. Soroka, A. G. Sokolov, S. O.Shurchkov*, D. A. Kazancev, P. E. Afanasenko, Moscow State Institute of Electronic Engineering, Russia
  
• * "International Computer Initiative" Scientific Centre, Russia
  
• General Discussion
  

Conclusions