The approval of the Verilog hardware description language as the IEEE 1364 standard underscores the importance and status of this language as a key EDA tool. For many digital systems, the design path relies on synthesis tools to implement a realization of a HDL description. Many of today's design flows for ASICs and FPGAs typically rely on synthesis tools that optimize and map Verilog HDL descriptions into physical netlists, thereby reducing the design cycle while increasing the opportunity for design exploration. The growing acceptance of this design paradigm suggests that an increasing number of designers well need to know how to be productive users of Verilog in the future.
HDLs are not the same as procedural programming languages. They require the user to appreciate hardware-related semantics and syntax, but they also require the user to become familiar with notions of event-driven simulation and concurrency in non-procedural language-based descriptions of digital circuits.
This presentation will describe the technical details of the Verilog HDL. It will acquaint workshop attendees with the language and illustrate its utility and ease of use by presenting several examples of combinational and sequential circuits.
1. Introduction and Motivation
2. Technical Overview of Verilog HDL
3. Modeling with the Verilog HDL
4. Examples
Prof. Michael D. Ciletti
Dept. of Electrical and Computer Engineering
Univ. of Colorado at Colorado Springs
P.O. Box 7150
Colorado Springs, Colorado 80933-7150
E-mail: ciletti@vlsic.uccs.edu
