System designers need accurate models of new CPUs a year before first silicon. Logic model developers are impeded by having to support multiple modeling languages, platforms and simulators. The situation is similar in the signal integrity arena, where SPICE models have historically required the disclosure of proprietary design and fabrication information, and where multiple modeling language dialects also exist. The component modeler must track component specifications as they evolve, validate the models for every platform and distribute them in a way that protects the IC vendor's intellectual property. This paper describes the key problems faced by the model provider, and discusses two initiatives, the EIA IBIS Open Forum for signal integrity models, and the Open Model Forum for logic models. Widespread adoption of these standards will mean that semiconductor companies can deliver the information once, EDA tools have a ready and easy source for models, and end users gain high-performance, accurate models when needed.
