Testing systems using a standard test bus is presently the best method to guarantee the necessary test compatibility between IC manufacturers. A first action to promote a test bus started in 1985 in Europe with the Joint Test Action Group, JTAG. A test bus called IEEE1149.1 is now widely supported by most semiconductor companies, system test companies and a growing number of system designers. The success of this action and the increasing need in testing mixed-signal and state-of-the-art systems has accelerated the process development of new standard test busses. Boundary-Scan technique answers the test problem at the IC, Multi-Chip Module, PCB, and complete hardware system levels. More recently, it has addressed module test and maintenance. A mixed analog-digital system test is coming soon. By its standard feature, the Boundary-Scan architecture can be easily automatically included in designs by synthesis tools, even at high levels of abstraction.
The benefit of this technique will reach its maximum when all chips in the system to test are 100% Boundary-Scan compatible. Although many techniques mixing Boundary-Scan with non Boundary-Scan chips have been proved technically feasible and cost effective.
Finally, the transition from in-circuit to Boundary-Scan test is already a success. The rapidly growing Boundary-Scan market testifies, if necessary, to all the benefits of the Boundary-Scan technique.
This course will give participants an overview of the test standard family and the present situation and advances.
Adam Osseiran is a Professor of microelectronics at the Engineering School of Geneva. He is doctor in microelectronics from the INPG, National Polytechnic Institute if Grenoble-France since may 1986, where he worked in the TIMA group. He spent nine years at the EPFL, National Polytechnic Institute of Lausanne-Switzerland working in fields like ASIC design and design for testability. He is a representative in Europe of the Working Group in the standardisation of the IEEE1149.4 mixed-signal test bus.
Dr. Adam Osseiran
EPFL - LEG/C3i
Swiss Federal Institute of Technology
Electrical Engineering Department
CH-1015 Lausanne, Switzerland
E-mail: osseiran@leg.de.epfl.ch
Phone: +41(21)693 69 90 (Central European Time)
Fax : +41(21)693 47 35
