Abstract:
Component Modelling Conventions and Standards

The presentation will be structured in two major parts, Coding Standards for VHDL and Models for Board-level Simulation. In the first part the following topics will be discussed:

The second part will discuss component models for Board-Level Simulation. It will not be limited to VHDL, but cover general aspects and requirements for this type of models:

The course material will consist of:

Peter Sinander

Peter Sinander is leading the work at the Microelectronics and Technology section at the European Space Research and Technology Centre (ESTEC), the main technical centre of the European Space Agency (ESA). ESA is an organisation of 14 European member states with Canada as an associate member, with the charter to develop space applications for peaceful purposes.

The Microelectronics and Technology section deals with design of ASICs and ASSPs (i.e. ASICs to be used by several companies as a standard product), and ASIC design methodology including VHDL modelling. Projects include:

For more information see the ESA Microelectronics page

Contact

Peter Sinander
Microelectronics and Technology section (WSM)
European Space Agency
European Space Research & Technology Centre
PO Box 299
2200 AG Noordwijk
The Netherlands

Phone: +31-71-565 33 67
Fax: +31-71-565 42 95
WWW: http://www.estec.esa.nl/wsmwww/
E-mail: psi@ws.estec.esa.nl